1. Field of the Invention
The present invention relates generally to electronic, peak detect-and-hold circuits and more particularly to a two-phase, peak detect-and-hold circuit, which is able to cancel offset voltages and sense rail-to-rail input signals.
2. Description of the Prior Art
In many signal processing applications, it is necessary to record the peak value of a time-varying waveform. The current state of the art in integrated peak detectors in CMOS (complementary metal-oxide semiconductor) devices suffers from two major limitations: offset voltage and the inability to process signals over the full range of the supply voltage. Both of these problems affect the performance of the circuit more acutely in modem low-voltage CMOS technologies.
In high sampling rate systems with randomly arriving signals, peak detectors suffer from an inherent inefficiency. A conventional peak detector is insensitive to the input from the time a peak is detected until the held voltage is read out and converted by an ADC (analog-to-digital converter), which provides a reset signal for a capacitor storing the held voltage.
Pulses that arrive during this interval are not recorded by the system, and the quantity of these unrecorded pulses cannot be monitored. To minimize this inefficiency, the speed of acquiring readout data must be increased in order to keep up with the minimum inter-arrival time of the input pulse stream. However, acquisition speed is severely limited by technology and the tolerance to increases in the cost of the ADC.
It is an object of the present invention to provide a peak detect-and-hold circuit that is able to substantially cancel offset voltage and common-mode rejection error.
It is a further object of the present invention to provide a peak detect-and-hold circuit that is able to sense rail-to-rail input signals.
It is another object of the present invention to provide a peak detect-and-hold circuit that may readily be modified to detect positive, negative, or peak-to-peak voltages.
It is still a further object of the present invention to provide a two-phase, peak detect-and-hold circuit that is able to automatically switch from a detect-and-hold phase to a readout phase.
It is still another object of the present invention to provide a peak detect-and-hold circuit that provides analog buffering.
It is yet a further object of the present invention to provide a peak detect-and-hold circuit that includes derandomizing architecture that circumvents restrictions on the speed of acquiring randomly distributed input signals.
A two-phase peak detect-and-hold circuit formed in accordance with one form of the present invention, which incorporates some of the preferred features, includes an amplifier, three switches, a transistor, and a capacitor. The first switch is connected between an input voltage signal and an inverting input terminal of the amplifier. The third switch is connected between an output terminal of the amplifier, which provides an output voltage, and a gate of the transistor. The second switch is connected between the inverting input terminal of the amplifier and its output terminal, and the non-inverting input terminal of the amplifier is connected to a drain of the transistor. The capacitor is connected in series between the non-inverting input terminal and ground. The source of the transistor is preferably connected to a voltage source.
During a detect-and-hold phase, the first and third switches are preferably closed and the second switch is preferably open. In this phase, a hold voltage at the non-inverting input terminal of the amplifier tracks the input voltage signal and when a peak is reached, the transistor is switched off, thereby storing a peak voltage in the capacitor.
During a readout phase, the first and third switches are preferably open and the second switch is preferably closed. In this phase, the circuit functions as a unity gain buffer, in which the voltage stored in the capacitor is provided as the output voltage. Thus, despite voltage dependencies, the circuit formed in accordance with the present invention is able to cancel offset voltage and common-mode rejection errors.
The circuit is able to sense signals rail-to-rail and can readily be modified to sense positive, negative, or peak-to-peak voltages. Derandomization may be achieved by using a plurality of peak detect-and-hold circuits suitably connected in parallel. A second embodiment of the peak detect-and-hold circuit formed in accordance with one form of the present invention, which incorporates some of the preferred features, includes a plurality of capacitors suitably connected in parallel to achieve substantial savings in power.
These and other objects, features, and advantages of this invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawing.